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Ultra Low Output Voltage Dual Linear FET Controller
POWER MANAGEMENT Description
The SC338(A) is an ultra low output voltage dual power supply controller designed to simplify power management for notebook PCs. It is part of Semtech's Smart LDOTM family of products. The SC338(A) has two user adjustable outputs that can be set anywhere between 0.5V and 3.3V (VIN = 12V, anywhere between 0.5V and 1.8V for V IN = 5V) using two external resistors per output. SC338(A) features for each output include tight output voltage regulation (2.5% over -40C to +85C for SC338, 1.5% over 0C to +85C for SC338A), enable controls, open drain power good signals, under-voltage protection and soft start. The enable pins allow the part to enter a very low power standby mode. Pulling them high enables the outputs. The power good pins are open drain and assert low when the voltage at their respective adjust pins is below 88% (typ.) of nominal. If the voltage at the adjust pin is below 50% (typ.) of nominal, the under voltage protection circuitry will shut down that output. The SC338(A) is available in an MSOP-10 surface mount package.
SC338(A)
Features
1.5% and 2.5% reference voltage options available Two independant and fully adjustable outputs Wide supply voltage range permits operation from 5V or 12V rails Very low quiescent current (500A typical with both outputs enabled and 5V input) Indivdual Enable control for each output Individual Power Good monitoring and signalling for each output Gate drives from input supply enable use of N-channel MOSFETs User selectable dropout voltage Individual under-voltage protection for each output MSOP-10 surface mount package
Applications
Notebook PCs Simple dual power supplies
Typical Application Circuit
5V or 12V IN
1.2V +/-5% IN C1 0.1uF (1) 8 1 C3 Q1 IRF7311 or similar 2 4 7 6 5 3 C4 C2 0.1uF (1)
1.8V +/-5% IN
1.05V @ 3A
1.5V @ 1.5A
100uF, 25mOhm POSCAP
R1 11.0k
R5 2k (2)
1 2
U1 DRV1 ADJ1 EN1 PGD1 GND
SC338(A) IN DRV2 ADJ2 EN2 PGD2
10 9 8 7 6 C6 0.1uF C7 10nF (2) R6 2k (2)
R3 20.0k
100uF, 25mOhm POSCAP
1.05V Enable 1.05V Power Good
3 4 5 R2 10.0k C5 10nF (2)
1.5V Enable 1.5V Power Good R4 10.0k
R1 VOUT1 = 0.5 * 1 + R2
Revision: November 12, 2004
Notes: (1) Additional capacitance may be required if far from supply (2) Optional soft-start components
R3 VOUT 2 = 0.5 * 1 + R4
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SC338(A)
POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter Input Supply Voltage Drive Pins Adjust and Power Good Pins Enable Pins Thermal Impedance Junction to Ambient Thermal Impedance Junction to Case Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol VIN VDRV VADJ, VPGD V EN J A J C TA TJ TSTG TLEAD V ESD
Maximum -0.3 to +13.2 -0.3 to +8.0 -0.3 to +5.5 -0.3 to VIN 113 42 -40 to +85 -40 to +125 -65 to +150 300 2
(1)
Units V V V V C/W C/W C C C C kV
Note: (1) Or VIN, if VIN = 5V.
Electrical Characteristics
Unless specified: TA = 25C, VIN = VEN = 5V 5%, VPWR(1) = 1.5V 5%, 0A IOUT 3A. Values in bold apply over full operating ambient temperature range.
Parameter IN Supply Voltage Quiescent Current
Symbol
Test Conditions
Min
Typ
Max
Units
VIN IQ VIN = 5V VIN = 12V
4.5 500 600 0.1
13.2 700 900 1.0 15.0
V A A A
Standby Current
IQ(OFF)
Both EN low Both EN low, VIN = 12V
Undervoltage Lockout Start Threshold Hysteresis EN Enable Input Threshold VIH VIL Output on Output off 1.3 0.7 V VUVLO VHYST VIN rising VIN falling 3.75 0.50 V V
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SC338(A)
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C, VIN = VEN = 5V 5%, VPWR(1) = 1.5V 5%, 0A IOUT 3A. Values in bold apply over full operating ambient temperature range.
Parameter EN (Cont.) Enable Input Bias Current
Symbol
Test Conditions
Min
Typ
Max
Units
IEN
V E N = 0V VIN = VEN = 5V or 12V -1
0 +1
A
ADJ Adjust Input Bias Current Reference Voltage IADJ V AD J SC338A only: 0C TA +85C DRV Output Current IDRV Sourcing, startup (until VTH(PGD) is reached) Sourcing, after startup Sinking Output Voltage VDRV Full On, IDRV = 0mA, VIN = 12V Full On, IDRV = 0mA, VIN = 5V Under Voltage Protection Trip Threshold PGD Power Good Threshold
(3) (2)
VADJ = 0.5V
-100 -2.5% -1.5%
0 0.500
+100 +2.5% +1.5%
nA V
10 0.7 400 6.6 4.70 2.0 750 6.9 4.85
A mA A V
VTH(UV)
Measured at ADJ pin
40
50
60
%VADJ
VTH(PGD) VPGD IPGD
Measured at ADJ pin VADJ = 0.4V, IPGD = -1mA VADJ = 0.5V, 0V VPGD VIN
-15
-12
-9 0.4
%VADJ V A
Output Logic Low Voltage Power Good Leakage Current Soft Start Output Rise Time 10% VOUT to 90% VOUT, VOUT = 1.05V
-1
0
+1
tr
CDRV-GND = not placed CDRV-GND = 10nF
150 850
s
Notes: (1) VPWR = input voltage to pass device drains (or sources depending upon orientation of FETs). (2) If VTH(UV) is exceeded for longer than 50s (nom.) the protection circuitry will shut down that output. (3) During startup only, VTH(PGD) is -6% (typ.), then switches to -12% (typ.).
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SC338(A)
POWER MANAGEMENT Pin Configuration
Top View
PRELIMINARY Ordering Information
Part Number(1) SC338IMSTR(3) SC338IMSTRT(3)(5) SC338AIMSTR(4) SC338AIMSTRT(4)(5) Output Voltage(2) Both outputs adjustable from 0.5V to 3.3V P ackag e MSOP-10
(MSOP-10)
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) VIN = 12V (0.5V to 1.8V for VIN = 5V). (3) VADJ is 2.5% over -40C TA +85C. (4) VADJ is 1.5% over 0C TA +85C. (5) Lead free product. This product is fully WEEE and RoHS compliant.
Pin Descriptions
Pin 1 2 Pin Name Pin Function DRV1 A D J1 Output of regulator #1. Drives the gate of an N-channel MOSFET to maintain VOUT1 set by R1 and R2. Regulator #1 sense input. Used for sensing the output voltage for power good and under-voltage, and to set the output voltage as follows (refer to application circuit on page 1): R1 VOUT1 = 0.5 * 1 + R2 VOUT(MAX) = 3.3V for VIN = 12V, 1.8V for VIN = 5V. Active high enable control. Connect to IN if not being used. Do not allow to float. Power good signal output for VOUT1. Open drain output pulls low when VOUT1 is below (VOUT1(NOM) -12%). Ground. Power good signal output for VOUT2. Open drain output pulls low when VOUT2 is below (VOUT2(NOM) -12%). Active high enable control. Connect to IN if not being used. Do not allow to float. Regulator #2 sense input. Used for sensing the output voltage for power good and under-voltage, and to set the output voltage as follows (refer to application circuit on page 1): R3 VOUT 2 = 0.5 * 1 + VOUT(MAX) = 3.3V for VIN = 12V, 1.8V for VIN = 5V. R4 Output of regulator #2. Drives the gate of an N-channel MOSFET to maintain VOUT2 set by R3 and R4. +5V or +12V supply.
3 4 5 6 7 8
EN1 PGD1 GND PGD2 EN2 A D J2
9 10
DRV2 IN
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SC338(A)
POWER MANAGEMENT Block Diagram
(0.95 VBG at start-up)
(0.95 VBG at start-up)
Marking Information
SC338 Top Mark
AK00 yyww
SC338A
Top Mark
AK0A 338A yyww
Bottom Mark
xxxx xxxx
Bottom Mark
xxxx xxxx
AK00: yyww: xxxx: xxxx:
Identifier for SC338 Date code (Example: 0012) Semtech Lot # (Example: E901 01-1)
338A: yyww: xxxx: xxxx:
Identifier for SC338A Date code (Example: 0012) Semtech Lot # (Example: E901 01-1)
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SC338(A)
POWER MANAGEMENT Applications Infomation
Theory Of Operation The SC338(A) dual linear FET controller provides a simple way to drive two N-channel MOSFETs to produce tightly regulated output voltages from one or two available, higher, supply voltages. It takes its power from either a 5V or 12V supply, drawing typically 500A while operating. It contains an internal bandgap reference which is compared to the output voltages via resistor dividers. These resistor dividers are external and user selectable . Depending upon the input voltage used for the device, the drive pin (DRV1, DRV2) can pull up to a guaranteed minimum of 6.6V (from 12V supply) or 4.7V (from 5V supply). Thus the device can be used to regulate a large range of output voltages by careful selection of the external MOSFETs (see component selection, below). The SC338(A) includes an active high enable control (EN1, EN2) for each output. If this pin is pulled low, the related drive pin is pulled low, turning off the N-channel MOSFET. If the pin is pulled up to 1.8V VEN VIN, the drive pin will be enabled. This pin should not be allowed to float. Each output has a power good output (PGD1, PGD2) which are open drain outputs that pull low if the related output is below the power good threshold (-12% of the programmed output voltage typical, -6% typical at startup). The power good circuitry is active if the device is enabled, regardless of the state of the over current latch. The power good circuitry is not active if that particular output is disabled. Also included for each output is an overcurrent protection circuit that monitors the output voltage. If the output voltage drops below 50% (typ.) of nominal, as would occur during an overcurrent or short condition, the device will pull the drive pin low and latch off. The device will need to have the power supply or enable pin toggled to reset the latch condition. Each output latches independently (i.e. if one output latches off, the other output will function normally). Drive Outputs and Soft Start The drive outputs for each output are source and sink capable. The sink current is typically 0.8mA at 5V in (1mA at 12V in). The source current is typically 2mA at 5V in
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PRELIMINARY
and 3.75mA at 12V in during normal operation. The high side drive voltage is generated from VIN by a 7V (nominal) low dropout regulator, thus at 12V in, 6.9V is available and at 5V in, 4.85V is available (since the LDO will be in dropout). At start-up, the source current available from the drive pins is limited to 10A (typical) until the power good threshold is reached, at approximately 6% below nominal output voltage. At this point the full drive capability is enabled. With this constant current source at start-up, it is a simple matter to use a small capacitor on the drive pin to slow this rate of rise. The rate of rise of the drive pin voltage will be:
dVDRV IDRV = V/s dt CSS
A 10nF soft start capacitor will give a 1ms output rise time for VIN = 12V and VOUT = 1.05V, for example. The output rise time will of course depend upon the gate threshold of the MOSFET being used. Please refer to the Output Rise Time chart on Page 13 showing typical output rise times. For very low ESR output capacitors (<5m) and very high soft start capacitance (>100nF), it may be necessary to add a resistor in series with the soft start capacitor to ensure stability. Generally, however, this resistor is not required, as this is a very unlikely situation. The soft start capacitance does not adversely affect transient response since the drive current capability is 200 times higher once the device has started. OCP and Power Supply Sequencing The SC338(A) has output undervoltage protection that looks at a particular output to see if it is a) less than 50% (typical) of it's nominal value and b) VDRV for that output is within 350mV (typical) of maximum. If both of these criteria are met, there is a 50s (typical) delay and then the output is shut down. This provides inherent immunity to UV shutdown at start-up (which may occur while the output capacitors are being charged) since VDRV has a very slow rate of rise with IDRV limited to 10A. At start-up, it is necessary to ensure that the power supplies and enables are sequenced correctly to avoid erroneous latch-off. For UV latch-off not to occur at startup due to sequencing issues, the key is that the voltage
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SC338(A)
POWER MANAGEMENT Applications Infomation (Cont.)
supplied to the MOSFET drain should be greater than the output undervoltage threshold when that output is enabled. This assumes that the drop through the pass MOSFET is negligible. If not, then this drop needs to be taken into account also since: VOUT = VDRAIN - (IOUT x RDS(ON)). If the supply to the SC338(A) IN pin comes up before the supply to the MOSFET drain, then that output should be enabled as the supply to the MOSFET drain is applied - the Power Good signal for this rail would be ideal. If the power supply to the MOSFET drain comes up before the power supply to the SC338(A) IN pin, then the output can either be enabled with the supply to the IN pin or afterwards. Please see the example below. Example: SC338(A) powered from 5V, output 1 powered from 1.8V set for 1.5V out, output 2 not shown for simplicity. Worst case undervoltage threshold is 60% (over temperature) of 1.5V, or 0.9V. The typical enable threshold is ~1V. See Figure 1 below. Component Selection Output Capacitors: low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps are recommended for bulk capacitance, with ceramic bypass capacitors for decoupling high frequency transients. Input Capacitors: placement of low ESR capacitors such as Sanyo POSCAPs or Panasonic SP-caps at the input to the MOSFET (VDRAIN) will help to hold up the power supply during fast load changes, thus improving overall transient response. If VDRAIN is located at the bulk capacitors for the upstream voltage regulator, additional capacitance
SC338(A) Supply Comes Up Before MOSFET Drain Supply
MOSFET Drain Supply Comes Up Before SC338(A) Supply Figure 1: Power Supply Sequencing
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SC338(A)
POWER MANAGEMENT Applications Infomation (Cont.)
may not be required. In this case a 0.1F ceramic capacitor will suffice. The input supply to the SC338(A) should be bypassed with a 0.1F ceramic capacitor. MOSFETs: very low or low threshold N-channel MOSFETs are required. Selecting FETs rated for VGS of 2.7V or 4.5V will depend upon the available drive voltage (6.9V from 12V in or 4.85V from 5V in), the output voltage and output current. For the device to work under all operating conditions, a maximum RDS(ON) must be met to ensure that the output will never go into dropout:
RDS( ON)(MAX ) = VIN(MIN ) - VOUT (MAX ) IOUT (MAX )
VOUT (V) 1.05 1.2 1.5 2.5 3.3 R1 or R3 (k ) 11.0 14.0 20.0 45.3 63.4
PRELIMINARY
R2 or R4 (k ) 10.0 10.0 10.0 11.3 11.3
Table 1: Recommended Resistor Values For SC338(A) Design Example Goal: 1.05V5% @ up to 2.5A from 1.2V5% and 5V5% Solution 1: no passive droop. Total window for DC error, ripple and transient is 52.5mV Since this device is linear, and assuming that it has been designed to not ever enter dropout, we do not have ripple on the output. The DC error for this output is the sum of: VREF accuracy = 2.5% = 26.3mV Feedback chain tolerance = 1% = 10.5mV Load regulation = 0.25% = 2.6mV Set resistors per Table 1 should be 11.0k (top) and 10.0k (bottom). Total DC error = 3.75% = 39.4mV This leaves 1.25% = 13.1mV for the load transient ESR spike, therefore:
Note that RDS(ON) must be met at all temperatures and at the minimum VGS condition. Setting The Output Voltage: the adjust pins connect directly to the inverting input of the error amplifiers, and the output voltage is set using external resistors (please refer to the Typical Application Circuit on page 1). Using output 1 as an example, the output voltage can be calculated as follows:
R1 VOUT = 0.5 * 1 + R2 The input bias current for the adjust pin is so low that it can be safely ignored. To avoid picking up noise, it is recommended that the total resistance of the feedback chain be less than 100k.
Please see Table 1 on this page for recommended resistor values for some standard output voltages. All resistors are 1%, 1/10W. The maximum output voltage that can be obtained from each output is determined by the input supply voltage and the R DS(ON) and gate threshold voltage of the external MOSFET. Assuming that the MOSFET gate threshold voltage is sufficiently low for the output voltage chosen and the worst-case drive voltage, VOUT(MAX) is given by:
VOUT (MAX ) = VDRAIN(MIN ) - IOUT (MAX ) * RDS( ON)(MAX )
13.1mV = 5.2m 2 .5 A Bulk capacitance required is given by: RESR(MAX ) =
dI * t F dV Where dI is the maximum load current step, t is the maximum regulator response time and dV is the CBULK (MIN ) =
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SC338(A)
POWER MANAGEMENT Applications Infomation (Cont.)
allowable voltage droop. Therefore with dI = 2.5A, t = 1s, and dV = 13.1mV: Solution 2: using passive droop.
2.5 * 1 * 10 -6 = 191F 13.1 * 10 -3 So if we use 1% VOUT set resistors we would select 2 x >100F, 12m POSCAPs for output capacitance (which assumes that local ceramic bypass capacitors will absorb the balance of the (6 - 5.3)m ESR requirement - otherwise 10m capacitors should be used). CBULK (MIN) =
If we use 0.1% set resistors, then the total DC error becomes 2.85% = 29.9mV, leaving 2.15% = 22.6mV for the ESR spike. In this case:
1.2V +/-5% IN
C1 0.1uF 8 RDROOP 1.075V C3 20mOhm 1 7 6 5 3
1.05V @ 2.5A
Q1 IRF7311 or similar 2 R1 1 2 3 R2 10.0k 4 5 U1 DRV1 ADJ1 EN1 PGD1 GND 4 SC338(A) 10 IN 9 DRV2 8 ADJ2 7 EN2 6 PGD2
100uF, 25mOhm POSCAP
11.0k
RESR(MAX ) = CBULK (MIN) =
22.6mV = 9.0m and 2 .5 A
2.5 * 1 * 10 -6 = 111F 22.6 * 10 -3 So for 0.1% resistors we could use 2 x 100F, 18m POSCAPs for output capacitance, or 1 x >100F, 10m POSCAP.
Obviously this is a very severe example, since the output voltage is so low and therefore the allowable window is very small. See solution 2 below for an alternate solution. For higher output voltages the components required will be less stringent. The input capacitance needs to be large enough to stop the input supply from collapsing below -5% (i.e. the design minimum) during output load steps. If the input to the pass MOSFET is not local to the supply bulk capacitance then additional bulk capacitance may be required. MOSFET selection: since the input voltage to the SC338(A) is 5V5%, the minimum available gate drive is:
VGS = ( 4.4 - 1.1025 ) = 3.3 V So a MOSFET rated for VGS = 2.7V will be required, with an RDS(ON)(MAX) (over temp.) given by:
Passive droop allows us to use almost the full output tolerance window for transients, hence making the output capacitor selection simpler and (hopefully) cheaper. The trade-offs are the cost of the droop resistor versus the reduction in output capacitor cost, and the reduction in headroom which impacts MOSFET selection. The top of the feedback chain connects to the "input" side of RDROOP, and the output is set for 1.075V. Thus at no load, VOUT will be 1.075V (or 1.05V + 2.4%) and at IOUT = 2.5A, VOUT will be 1.025V (or 1.05V - 2.4%). If 1% set resistors are used, the total DC error will be 3.75% = 39mV. Thus at no load, the minimum output voltage will be given by:
VOUT (MIN _ NO _ LOAD ) = 1.075 - 0.039 = 1.036 V
This leaves 38.5mV for transient response, giving:
RESR(MAX ) =
CBULK (MIN) =
38.5mV = 15.4m and 2.5 A
2.5 * 1 * 10 -6 = 65F 38.5 * 10 -3 Instead of 2 x 100F, 12m capacitors, we can use 1 x 100F, 15m capacitor.
Layout Guidelines The advantages of using the SC338(A) to drive external MOSFETs are a) that the bandgap reference and control circuitry are in a die that does not contain high power dissipating devices and b) that the device itself does not
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RDS( ON)MAX ) =
( VIN(MIN ) - VOUT ) IOUT (MAX )
=
(1.14 - 1.05 ) = 36m 2. 5
Obviously, if a 12V rail is available to power the SC338(A), the number of FET options increases dramatically.
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SC338(A)
POWER MANAGEMENT Applications Infomation (Cont.)
need to be located right next to the power devices. Thus very accurate output voltages can be obtained since changes due to heating effects will be minimal. The 0.1F bypass capacitor should be located close to the supply (IN) and GND pins, and connected directly to the ground plane. The feedback resistors should be located at the device, with the sense line from the output routed from the load (or top end of the droop resistor if passive droop is being used) directly to the feedback chain. If passive droop is being used, the droop resistor should be located right at the load to avoid adding additional unplanned droop. Sense and drive lines should be routed away from noisy traces or components. For very low input to output voltage differentials, the input to output / load path should be as wide and short as possible. Where greater headroom is available, wide traces may suffice. Power dissipation within the device is practically negligible, thus requiring no special consideration during layout. The MOSFET pass devices should be laid out according to the manufacturer's guidelines for the power being dissipated within them.
PRELIMINARY
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SC338(A)
POWER MANAGEMENT Typical Characteristics
Quiescent Current vs. Junction Temperature vs. Input Voltage
900 800 700 600 IQ (A) 500 400 300 200 100 0 -50 -25 0 25 TJ (C) 50 75 100 125 0.01 -50 -25 0 25 TJ (C) 50 75 100 125 0.1 VIN = 5V VIN = 5V Both VEN = 5V Both VADJ < VBG VIN = 12V IQ(OFF) (A) 100 Both VEN = 0V VIN = 12V 10
Standby Current vs. Junction Temperature vs. Input Voltage
1
Start Threshold vs. Junction Temperature
5.0 4.5 4.0 3.5 VUVLO (V) VIH/L (V) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 TJ (C) 50 75 100 125 VIN falling VIN rising 1.8 1.6 1.4
Enable Input Threshold Voltage vs. Junction Temperature
VIN = 5V
VIH 1.2 1.0 0.8 0.6 0.4 -50 -25 0 25 TJ (C) 50 75 100 125
VIL
Reference Voltage vs. Junction Temperature
0.510 0.508 0.506 0.504 VADJ (mV) IDRV (A) 0.502 0.500 0.498 0.496 0.494 0.492 0.490 -50 -25 0 25 TJ (C) 50 75 100 125 VIN = VEN = 5V
Drive Pin Output Current (Sourcing) at Startup vs. Junction Temperature vs. Input Voltage
20 18 16 14 12 10 8 6 4 2 0 -50 -25 0 25 TJ (C) 50 75 100 125 VIN = 5V VIN = 12V VEN = 5V VADJ < VTH(PGD)
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SC338(A)
POWER MANAGEMENT Typical Characteristics (Cont.)
Drive Pin Output Current (Sourcing) vs. Junction Temperature vs. Input Voltage
5.0 4.5 4.0 3.5 IDRV (mA) IDRV (A) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 TJ (C) 50 75 100 125 0 -50 -25 0 25 TJ (C) 50 75 100 125 VIN = 5V 200 VIN = 12V VEN = 5V VADJ < VBG 1200 1000 800 600 400 VEN = 5V VADJ > VBG VIN = 12V
PRELIMINARY
Drive Pin Output Current (Sinking) vs. Junction Temperature vs. Input Voltage
VIN = 5V
Drive Pin Output Voltage (Full On) vs. Junction Temperature vs. Input Voltage
8 7 6 5 VDRV (V) 4 3 2 1 0 -50 -25 0 25 TJ (C) 50 75 100 125 VEN = 5V IDRV = 0mA VADJ < VBG VIN = 12V VTH(UV) (%VADJ) VIN = 5V -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -50
Under Voltage Trip Threshold vs. Junction Temperature
VIN = VEN = 5V
-25
0
25 TJ (C)
50
75
100
125
Power Good Threshold vs. Junction Temperature
0.0 VIN = VEN = 5V -2.5 VTH(PGD) (%VADJ) -5.0 -7.5 -10.0 -12.5 -15.0 -50 -25 0 25 TJ (C) 50 75 100 125 VPGD (mV) 175 150 125 100 75 50 Normal operation 25 0 200
Power Good Logic Low Output Voltage vs. Junction Temperature
VIN = VEN = 5V VADJ = 0.4V IPGD = -1mA
Startup only
-50
-25
0
25 TJ (C)
50
75
100
125
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SC338(A)
POWER MANAGEMENT Typical Characteristics (Cont.)
Output Rise Time At Startup vs. Soft Start Capacitance vs. Input Voltage
100 VEN = 5V TJ = 25C VOUT = 1.05V COUT = 100F, 25m IOUT = 0A MOSFET = IRF7311
10 tr(OUT) (ms)
1
VIN = 5V
VIN = 12V 0.1 0.1 1 CDRV (nF) 10 100
Load Transient Response, No Passive Droop
Load Transient Response, With Passive Droop
VIN = 5V, 1.2V in to 1.05V out IOUT = 0.01A to 2.51A to 0.01A COUT = 2 x 100F, 25m Trace 1: VOUT, 20mV/div., offset 1V Trace 2: VDRV, 2V/div. Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20s/div. Load rise/fall times 35A/s
VIN = 5V, 1.2V in to 1.05V out IOUT = 0.01A to 2.51A to 0.01A COUT = 1 x 100F, 25m RDROOP = 20m Trace 1: VOUT, 20mV/div., offset 1V Trace 2: not connected Trace 3: 1.2V in, 50mV/div., offset 1V Trace 4: load FET drain Timebase: 20s/div. Load rise/fall times 35A/s
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SC338(A)
POWER MANAGEMENT Outline Drawing - MSOP-10
e A N 2X E/2 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 B E1 E D
PRELIMINARY
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.043 .000 .006 .030 .037 .007 .011 .003 .009 .114 .118 .122 .114 .118 .122 .193 BSC .020 BSC .016 .024 .032 (.037) 10 8 0 .004 .003 .010 1.10 0.00 0.15 0.75 0.95 0.17 0.27 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.50 BSC 0.40 0.60 0.80 (.95) 10 0 8 0.10 0.08 0.25
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
D aaa C SEATING PLANE A2 C A1 bxN bbb C A-B D A GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW SEE DETAIL L H c
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION BA.
Land Pattern - MSOP-10
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .020 .011 .063 .224 (4.10) 2.50 0.50 0.30 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2004 Semtech Corp.
14
www.semtech.com

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